Utilize on-chip high-speed network (2D NoC) to innovatively realize ultra-high-bandwidth logic interconnection within FPGA

Achronix’s latest Speedster7t FPGA devices based on TSMC’s 7nm FinFET process incorporate a revolutionary new two-dimensional network-on-chip (2D NoC). The 2D NoC, like a highway network running on the FPGA programmable logic fabric, provides ultra-high bandwidth (~27Tbps) for data transfer between high-speed interfaces outside the FPGA and internal programmable logic.

Author: Huang Lun, Senior Field Application Engineer at Achronix

An example of using NoC to optimize encryption and decryption design

Achronix’s latest Speedster7t FPGA devices based on TSMC’s 7nm FinFET process incorporate a revolutionary new two-dimensional network-on-chip (2D NoC). The 2D NoC, like a highway network running on the FPGA programmable logic fabric, provides ultra-high bandwidth (~27Tbps) for data transfer between high-speed interfaces outside the FPGA and internal programmable logic.

Utilize on-chip high-speed network (2D NoC) to innovatively realize ultra-high-bandwidth logic interconnection within FPGA

Figure 1 Speedster 7t FPGA block diagram

The NoC uses a series of high-speed row and column network paths to distribute data throughout the FPGA, thereby distributing data traffic horizontally and vertically throughout the FPGA fabric. Each row or column in the NoC has two 256-bit, unidirectional, industry-standard AXI lanes that can operate at 512Gbps (256bit x 2GHz) in each direction.

NoCs offer several important advantages for FPGA designs, including:

• Improve design performance.
• Reduces idle logic resources, reducing the risk of place-and-route congestion in high resource-intensive designs.
• Reduce power consumption.
• Simplify logic design, and use NoC to replace traditional logic for high-speed interface and bus management.
• Enables a true modular design.

This article uses a specific FPGA design example to demonstrate the important role that NoC plays in the interconnection of logic within FPGAs. This design is mainly to realize the triple data encryption and decryption algorithm (3DES). This algorithm is a mode of the DES encryption algorithm. It applies the DES encryption algorithm three times to each data block, and increases the security by increasing the key length of DES.

In this FPGA design, we put the input and output pins in the four directions of the FPGA, up and down, left and right. The data coming in from the upper pin is decrypted by logic 1 and then sent to logic 2 through the blue line for encryption and then sent out from the lower pin. The data coming in from the left pin is decrypted by logic 3 and then sent to logic 4 through the red trace to be encrypted and then sent out from the right pin. as shown in picture 2.

Utilize on-chip high-speed network (2D NoC) to innovatively realize ultra-high-bandwidth logic interconnection within FPGA

Figure 2 3DES design (no NoC) back-end layout and wiring diagram

The problems encountered in this design are as follows:

• The connection delay between the encryption and decryption modules is too long. If the pipeline register is not added, the design performance will be greatly limited. However, since the bit width of the connection bus is 256 bits, adding several stages of pipeline registers will occupy a lot of additional register resources.

• The connection bus between the upper and lower modules and the connection bus between the left and right modules are crossed. If the design is a little more complicated, it may encounter local congestion in the layout and routing, which will greatly increase the layout and routing time of the tool.

The above two problems are also problems that the majority of FPGA designers will encounter more or less in complex FPGA design. The reason may be that the design is more complicated, or it may be the limitation of the hardware platform, or the design must be connected to peripherals in different locations. Caused by Hard IP.

The emergence of NoC has solved the problems we encountered above. NoC provides a bidirectional 288bit raw data mode for the interconnection of FPGA logic. Users can make logical direct connection or custom protocol interconnection through the 288bit signal.

Utilize on-chip high-speed network (2D NoC) to innovatively realize ultra-high-bandwidth logic interconnection within FPGA

Figure 3. Internal logic interconnection using 2D NoC

There are two network access points (NAPs) at each intersection of the NoC, and users can access their own logic to the NoC and interconnect them simply by instantiating the NAP primitives or macro definitions.

Utilize on-chip high-speed network (2D NoC) to innovatively realize ultra-high-bandwidth logic interconnection within FPGA

Figure 4 Network access point NAP

Utilize on-chip high-speed network (2D NoC) to innovatively realize ultra-high-bandwidth logic interconnection within FPGA Utilize on-chip high-speed network (2D NoC) to innovatively realize ultra-high-bandwidth logic interconnection within FPGA

Figure 5 Example of instantiated NAP macro definition

This enables NoC interconnection between the 3DES encryption and decryption modules by instantiating NAPs on the 3DES encryption and decryption modules, respectively.

Utilize on-chip high-speed network (2D NoC) to innovatively realize ultra-high-bandwidth logic interconnection within FPGA

Figure 6 3DES design (using NoC) back-end layout and routing diagram

In this way, while simplifying the user’s design, the design performance has been greatly improved, from the previous 260MHz to 750MHz. In Figure 6, it can be seen that a large number of connection buses between the logics have not been seen before, and the connections of the buses are taken over by the NoC. In the back-end layout and wiring diagram, only the green clock traces and the logic traces inside the white module can be seen .

This article mainly wants to show the majority of FPGA designers how to use NoC to interconnect the internal logic of the FPGA through such an example, so as to provide the majority of FPGA designers with another way of thinking about the problem. In the traditional FPGA design, when the performance cannot be improved and the layout and routing are congested, can we consider using Achronix’s new generation of Speedster7t FPGA to simplify and accelerate the user’s design.

This official account will also launch a series of articles on two-dimensional network-on-chip (NoC) in the future, such as the development of NoC technology, NoC performance evaluation and comparison with traditional interconnect architecture, technical parameters and calling methods of NoC in Speedster7t FPGA, Please look forward to the various reference designs of the NoC and more.

The Links:   G133IGE-L03 LQ080V3DG01

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