“The digital signal may be affected by various interferences and unsatisfactory channel transmission characteristics during the transmission process, causing errors in the signal and receiving wrong information. In order to realize the reliability of the digital system in the transmission process, almost all modern communication systems regard error correction coding as a basic component. Reed-So lomon (RS) code is currently one of the most effective and widely used error control codes. It is a type of multi-system BCH code with strong error correction capability. It can correct both burst errors and Random errors.

“

Authors: Dong Huaiyu, Yu Ningmei, Gao Yong, Liu Gaohui, Niu Lanqi, Chen Jingjin

The digital signal may be affected by various interferences and unsatisfactory channel transmission characteristics during the transmission process, causing errors in the signal and receiving wrong information. In order to realize the reliability of the digital system in the transmission process, almost all modern communication systems regard error correction coding as a basic component. Reed-So lomon (RS) code is currently one of the most effective and widely used error control codes. It is a type of multi-system BCH code with strong error correction capability. It can correct both burst errors and Random errors. RS codes are mainly used in high real-time mobile communication systems, deep space communications, digital satellite television, magnetic recording systems, etc.

The current design of RS encoders is mainly limited to the design of RS encoders with a single code length and fixed error correction capability. The RS encoder with variable code length and adjustable error correction capability proposed in this paper combines the commonly used RS (7, 3) code, RS (15, 11) code, and RS (15, 9) code in an encoding circuit. In this way, it can be made into an IP core, which can greatly reduce the area of the chip and provide convenience to users, as well as a lot of room for choice. The coding circuit adopts the m-bit fast finite field multiplication method based on the polynomial multiplication theory GF (2m), which greatly improves the coding speed of the circuit. The highest working frequency of the encoder designed in this paper can reach 100MHz, which fully meets the requirement of several hundred kbps for the data transmission rate of voice communication and data communication in wireless communication.

**Encoding algorithm selection**

Generally speaking, the RS code can be represented by three parameters (n, k, t), where n is the length of the codeword, k is the length of the information bit, and t is the error correction capability, which satisfies the relationship: t= (n-k) /2. All elements of the RS code are defined on GF (2m), where: m = log2n. For different m corresponds to a primitive polynomial, the elements of the finite field can be obtained from the primitive polynomial.

The limited fields of RS (7, 3) codes are shown in Table 1.

The generator polynomial of RS encoding is defined as:

So the generator polynomial of each code can be obtained:

RS (7, 3) code:

g (x) = x 4 + a3x 3 + x 2 + ax + a3

RS (15, 11) code:

g (x) = x 4 + a13x 3 + a6x 2 + a3x + a10

RS (15, 9) code:

g (x) = x 6 + a10x 5 + a14x 4 + a4x 3 + a6x 2 + a9x + a6

Use m (x) to represent the information codeword polynomial, and c (x) to represent the encoded codeword polynomial, then the encoding process of the RS code can be represented by the following encoding polynomial:

c (x) = m (x) x n- k +[m (x) x n- k]modg (x)

In the above formula,[m (x) x n- k]modg (x) is the remainder operation, and the check digit is obtained.

The hardware implementation process of the RS encoder is to use the circuit to complete the multiplication operation of the information bit polynomial k (x) and x n- k in the above-mentioned encoding polynomial and the remainder operation of k (x) x n-kmodg (x) . The composition and working principle of the encoding circuit will be discussed in detail below.

**Realization of encoding circuit**

The remainder operation of the RS encoding circuit can be implemented with n-k level shift registers, so 6 levels of shift registers can be selected; the number of information bits input is controlled by a counter, and a selection terminal can be added to control the counter. Which kind of code word is coded and counted; The output of information bit and check bit can be switched by a selector. So we can get the block diagram of the encoding circuit as shown in Figure 1.

In the circuit in Figure 1, all information data transmissions are 4-bit wide transmissions. Reset is the system reset signal. The working principle of the circuit is described as follows:

(1) When sel is set to 01, the encoding circuit is in the encoding state of RS (7, 3) code. Because the information of the RS (7, 3) code is represented by a 3-bit binary system, the highest bit of the data line is zero, and only the lower 3 bits are effective.

A. Before encoding, first give the circuit a reset signal to make the flip-flops in the counter and shift register in the zero state, and the reset adopts asynchronous reset.

B Input information (m 2 …, m 0 ), the counter starts counting, every time an information bit is input, the counter counts a number of times and then outputs it. At this time, the output of selector2 is connected to the output of the counter, so the information bits are output from the output of the encoding circuit on the one hand, and sent to the shift register circuit for remainder calculation on the other hand.

C When the 3 information bits are input, the counter outputs a control signal ct r, which is the output of the control information bits and check bits. At this time, the output of selcto r2 is connected to the output of selecto r1, and the two inputs of add5 Both ends are the output ends of selecto r1. Since the finite field addition does not consider the carry between bits, the output of add5 is 0, so the output of each multiplier mul is 0, so the check bit in the shift register will be output at one time . So the check digit (D 3,…, D 0) is output once. After the check bit is output, the register and the counter return to the zero state. Therefore, the encoded codeword is (m 2, ., m 0, D 3, …, D 0).

D Because the remainder operation of the RS (7, 3) code encoding circuit only needs 4-level shift registers to achieve, so switch K is turned off, and the next two levels of shift registers do not work, which reduces the power consumption of the circuit. The input terminal of A dd5 is connected to the output terminal of D3.

(2) When sel is set to 10, the encoding circuit is in the encoding state of RS (15, 11) code, and a reset signal must be given to the circuit before encoding. The process is the same as above, and the code word obtained after encoding is (m 10, …, m 0, D 3, …, D 0). Similarly, the remainder operation of the RS (15, 11) code encoding circuit only needs a 4-level shift register to achieve, so K is disconnected, and the input terminal of add5 is connected to the output terminal of D3.

(3) When sel is set to 11, the encoding circuit is in the encoding state of RS (15, 9) code. Before encoding, give the circuit a reset signal. After encoding, the codeword can be obtained as (m 8, …, m 0, D 3, …, D 0 ). The remainder operation of the RS(15, 9) code encoding circuit needs 6-level shift registers to implement. Therefore, K is turned on, and the input terminal of add5 is connected to the output terminal of D5.

In the coding circuit, the multiplier adopts the m-bit finite field multiplication method based on the polynomial multiplication theory GF (2m), which greatly improves the operation speed of the circuit.

**Fast finite field multiplier implementation:**

The realization idea of fast finite field multiplication is as follows, taking RS (7, 3) code as an example:

Therefore, a fast finite field multiplier can be realized, which greatly improves the operation speed of the circuit. Because RS (15, 11) code and RS (15, 9) code are based on the same finite field GF (24), their multipliers are the same. When sel is set to 01, the multiplier works in the multiplication state of GF (23), when sel is set to 10 or 11, the multiplier works in the multiplication state of GF (24). It’s just that when working in the GF (23) state, the 4th bit of the input and output of the multiplier is 0.

**Circuit simulation and testing**

The coding circuit module can be expressed as:

sel is the selection terminal of the encoding circuit, clk is the clock input terminal, reset is the system reset terminal, in is the information input terminal, and ou t is the code word output terminal.

After writing the code of the circuit in Verilog HDL language, use the NC Verilog HDL simulation tool of Cadence Company to simulate, and obtain the simulation results of various codes.

A) Give reset a reset signal to make the circuit in the zero state. When sel is set to 01, the input information circuit starts to encode. The input information bit is (0, 1, 2), and the parity bit (2, 3, 1, 3) is obtained after encoding, so the output code word at the output is (0, 1, 2, 2, 3, 1, 3) . Then input the information bit, and code it cyclically.

B) Give reset a reset signal, when sel is set to 10, the input information circuit starts to encode. The input information is (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A), and the check digit (C, E, 8, 3) is obtained after encoding, so the output codeword at the output is (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, C, E, 8, 3). Input the information again at the input, and code it cyclically. The output waveform is shown in Figure 4.

C) Give reset a reset signal, when sel is set to 11, the input information circuit starts to encode. The input information is (0, 1, 2, 3, 4, 5, 6, 7, 8), and the check digit (B, C, 0, 5, 7, 8) is obtained after encoding, so the output code word at the output is (0, 1, 2, 3, 4, 5, 6, 7, 8, B, C, 0, 5, 7, 8). Input the information again at the input, and code it cyclically.

After the simulation is completed, use Xilinx FPGA board, the main chip is SPARTAN II XC2SPQ 208 for verification, the input information is consistent with the simulation input information, and then use the logic analyzer to observe the output results.

A) After a reset signal is given to reset, the circuit works in the encoding state of RS (7, 3) code. The result of observing the input and output with a logic analyzer is shown in Figure 6 below. The dotted circle (0, 1, 2, 2, 3, 1, 3) represents a complete output code word.

B) First reset the circuit, and then let the circuit work in the encoding state of RS (15, 11) code. Use the logic analyzer to observe the input and output results as shown in Figure 7 below. The dotted circles are (0, 1, 2, 3) , 4, 5, 6, 7, 8, 9, A, C, E, 8, 3) represents a complete output code word.

C) After the circuit is reset, make it work in the encoding state of RS (15, 9) code. Use the logic analyzer to observe the result as shown in Figure 8 below. The dashed circle (0, 1, 2, 3, 4, 5, 6, 7, 8, B, C, 0, 5, 7, 8) represent a complete output codeword.

From the above simulation waveforms and test results, we can see that their output results are consistent, which verifies the correctness of the design.

**Circuit parameters**

After synthesizing the circuit code with the Pro ject Navigator synthesis tool of Xilinx Company, the equivalent gate unit number of the circuit is 1339; the static power consumption of the circuit is measured to be 12.50 mW, and the maximum operating frequency is 100 MHz.

**in conclusion**

A RS code encoder with variable code length and adjustable error correction capability is proposed. It solves the limitation that the previous RS encoder can only encode a single code length and fixed error correction capability. At the same time, it adopts a fast finite field multiplication method. Improve the calculation speed of the circuit. After the design, it was tested on the FPGA to verify the correctness of the design.

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