Performance characteristics, structure and application analysis of high-precision digital-to-analog converter TQ6124 chip

TQ6124 is a high-speed and high-precision digital-to-analog converter chip. It has 14 data bits and uses a segmented structure to divide the data bits into the highest 4 bits, the middle 3 bits and the lowest 7 bits. TQ6124 can use different digital-to-analog conversion methods for each segment of data. It integrates a high-precision current source and a high-precision resistor to ensure the accuracy of digital-to-analog conversion. The conversion speed of TQ6124 can reach 1GSa/s. The chip is flexible in design and easy to use. It only needs to add one or two integrated circuits and a small amount of peripheral circuits to form a complete digital-to-analog converter with high performance.

1 Introduction

TQ6124 is a high-speed and high-precision digital-to-analog converter chip. It has 14 data bits and uses a segmented structure to divide the data bits into the highest 4 bits, the middle 3 bits and the lowest 7 bits. TQ6124 can use different digital-to-analog conversion methods for each segment of data. It integrates a high-precision current source and a high-precision resistor to ensure the accuracy of digital-to-analog conversion. The conversion speed of TQ6124 can reach 1GSa/s. The chip is flexible in design and easy to use. It only needs to add one or two integrated circuits and a small amount of peripheral circuits to form a complete digital-to-analog converter with high performance.

2. Structural features and pin functions of TQ6124

2 . 1 Structure of TQ6124

TQ6124 is mainly composed of latch, encoder, delay device, current source, current switch array, R~2R resistor network and other circuits. Figure 1 shows a block diagram of its internal structure. The main features of TQ6124 are as follows:

●Digital-to-analog conversion rate up to 1GSa/s;

Performance characteristics, structure and application analysis of high-precision digital-to-analog converter TQ6124 chip

●Has 14 data bits;

●With 1G analog signal bandwidth;

●The output can be directly used as the front end of the radio frequency;

●Clock and digital data are at ECL level;

●Use 44-pin QFP package.

2.2 Pin description of TQ6124

Figure 2 is the pin arrangement diagram of TQ6124. The functions of each pin are described as follows (the numbers in parentheses are the pin numbers):

Vss (1, 11, 12, 33, 34, 44): digital power input terminal, usually connected to -5V. The bypass capacitor of the power filter should be as close as possible to the power pin and directly connected to the ground;

VAA (21, 23, 24): -12V analog power input;

DGND (6, 7, 8, 28, 29, 37, 40): digital ground;

AGND (13, 15, 18, 19): analog ground;

D13~D0: digital signal input terminal, D13 is the highest bit of data, D0 is the lowest bit of data;

CLK, NCLK (9, 10): differential clock input;

Performance characteristics, structure and application analysis of high-precision digital-to-analog converter TQ6124 chip

NV0, V0 (16, 17): analog signal output terminals, which are differential signals;

IREF(14): The reference current input terminal, directly connected to the analog ground, is the virtual current source of the switch array;

VSNS(20): Judging the voltage output terminal, there is output when the chip is working normally, and Vsns=VREF;

VREF(21): Voltage reference input terminal, generally designed to be -9V, when VREF=-9V, the peak-to-peak value of the output analog signal is 1V;

Midtrim (25): Adjust the voltage input of the middle data bit to adjust the waveform, optional;

Lsbtrim(26): Adjust the voltage input of the lower data bits to adjust the waveform, optional;

ECLref (27): Optional ECL level reference voltage input terminal. When the digital data and clock are at ECL level, this pin is suspended, and the chip can generate a voltage of -1.34V.

3. Peripheral circuit design of TQ6124

TQ6124 is flexible and convenient to use, only need a voltage reference chip, an operational amplifier and a small amount of peripheral circuits (as shown in Figure 3). The main purpose of these two integrated circuits is to provide reference voltages for digital-to-analog conversion chips. In a digital-to-analog converter, the accuracy, stability and jitter of the reference voltage have a great influence on the accuracy, stability and jitter of the generated analog signal. In particular, the 14-bit data bits of this chip are more sensitive to the performance of the reference voltage. AD586 is a voltage reference chip produced by AD Company, it has good performance, and the error peak-to-peak value is only 4μV, which can meet the reference voltage requirement of 14-bit precision of TQ6124. The output of the voltage reference (AD586) and the feedback output VSENSE of the chip can form a negative feedback circuit through the operational amplifier MC34071 to stabilize the VREF at -9V, which can further reduce the influence caused by the slight change of the external power supply, thereby ensuring Accuracy and stability of the output analog signal.

4. Application description

Although the TQ6124 is easy to use, it does not require harsh external conditions, and it is easy to debug. However, when designing the circuit, especially in the layout and wiring of the printed circuit board, we must pay attention to follow certain design rules, otherwise the interference may be very large, and in severe cases, the quality of the output analog signal will be very poor, and the signal noise ratio is very low. Therefore, the following aspects should be paid attention to when using:

Performance characteristics, structure and application analysis of high-precision digital-to-analog converter TQ6124 chip

(1) Decoupling of the power supply: Generally, when designing this circuit, the analog power supply, digital power supply, and clock power supply must use 0.01μF capacitors to bypass and decouple their respective grounds. The decoupling capacitor should be as close as possible to the input end of the chip power supply. It is best to use surface mount components to reduce the interference caused by the leads, and the capacitor and the chip should be on the same level to reduce parasitic inductance and capacitance.

(2) Ground processing: The analog ground, digital ground and clock ground should be connected separately, which helps to eliminate the interference between data and clock, and a multi-layer circuit board with a complete and independent ground plane should be used to ensure high speed signal integrity. The impedance between the planes should be as small as possible, and the AC and DC voltage difference between the two should be lower than 0.3V. Both the analog ground and the clock ground should be connected to the digital ground at a single point at the power input end. Usually, a magnetic bead connection or direct connection can be used to avoid interference between places.

(3) Termination of high-speed signals: In high-speed digital systems, the impedance mismatch on the transmission line will cause signal reflection. The method to reduce and eliminate reflection is to perform terminal impedance matching at the transmitting end or the receiving end according to the characteristic impedance of the transmission line, so that the source reflection coefficient or load reflection coefficient is close to zero. Therefore, the input high-speed ECL clock and high-speed ECL digital signal must be terminated before input to the chip to reduce reflection.

(4) Heat dissipation treatment: Due to the large power consumption of the TQ6124 chip, a heat sink must be added when designing the circuit to ensure that the chip can work normally.

(5) High-speed digital signal lines and clock lines should be kept away from analog signal lines as far as possible. Digital ground should be placed around digital signal lines. Similarly, analog ground should be placed around analog signal lines, and clock ground should be placed around clocks to avoid inter-signal. interference.

(6) All signal lines should be as short as possible. If the signal lines are too long, the crosstalk between the lines may be larger.

In addition, in the application process of the chip, special attention should be paid to: since the chip latches data on the falling edge of the clock, the timing relationship between the clock and the data is shown in Figure 4. Therefore, in order to ensure the correctness of the data The change of data is best done on the rising edge of the clock to ensure that the chip has enough settling time when sampling the data.

Performance characteristics, structure and application analysis of high-precision digital-to-analog converter TQ6124 chip

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