Framework simplifies specification model based on uvm

Framework simplifies specification model based on uvm

Adopting a coverage-driven approach simplifies test composition and employs up-front randomisation for efficient simulation and accelerated emulation, explained the company. It also enhances test content reuse through configurable scenario libraries and portability for SoC integration verification.

Although uvm is an effective standard for block-level verification, it is facing obstacles as designs grow in size. “As blocks and subsystems get larger and more complicated, composing test content for the uvm environment becomes more difficult and harder to scale,” explained Breker’s CEO David Kelf. Leveraging synthesis for test content generation can result in a 5x improvement in composition time for larger components and multi-IP subsystems, and there are also “significant coverage increases”. The company says that the SystemUVM framework makes this easily accessible for verification specialists with a minimal learning curve. According to Kelf, it will be responsible for “dramatically changing the nature of functional verification”.

The framwork layers uvm class libraries on to Accellera’s Portable Stimulus Standard (PSS) to provide the look and feel of SystemVerilog/uvm and its procedural use model. Models can be composed quickly, efficiently reused and maintained through the register access level (ral), a library of common verification functions and abstract path constraints.

SystemUVM code offers an alternative to generic PSS but is still built on the industry standard which targets uvm engineers.

The SystemUVM-based test suite synthesis allows the simplified generation of self-checking test content from a single abstract model complete with high level path constraints for manageable code. Synthesis AI planning algorithms allow for specification state-space exploration, uncovering complex corner-cases that lead to potential complex bugs.

The coverage-driven nature of the process eliminates the need for coverage models and post-execution coverage analysis that results in test respins. Test randomisation is performed before execution so that simulation is accelerated and emulation can be used without an integrated testbench simulator. The tests can also be reused in system verification via the synthesisable verification OS layer without any change or disruption to the uvm testbench.

SystemUVM is available now and included in the company’s test suite synthesis portfolio.


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