FFRZVS circuit design scheme for USB PD adapter

By combining interface signals and power in a single cable, USB has the potential to meet the need to simplify the design of miniature power adapters. Today, the fourth-generation Universal Serial Bus (USB) since its introduction in 1996 has standardized computer connectivity, replacing interfaces such as serial and parallel ports, and has become the preferred choice for charging a variety of portable devices cable.

Author: Wang Zan

By combining interface signals and power in a single cable, USB has the potential to meet the need to simplify the design of miniature power adapters. Today, the fourth-generation Universal Serial Bus (USB) since its introduction in 1996 has standardized computer connectivity, replacing interfaces such as serial and parallel ports, and has become the preferred choice for charging a wide variety of portable devices cable.

The gigabit speeds specified in USB 3.0 make this bus a strong contender to replace all types of cables associated with PCs and laptops, including monitors, external disk drives, printers, and scanners. On top of that, with the USB Power Delivery (USB PD) specification, USB also eliminates the power cord.

Developed in 2012 to create an interoperable charging standard for all USB devices, USB PD has now undergone its third revision. It has evolved into a charging application capable of powering hard drives, printers and similar devices with power levels up to 100 W and voltages between 5 and 20V. A USB cable may soon be the only thing needed to power a laptop and connect various peripherals to it. By breaking the 7.5 W power limit at 5V, USB PD also opens up the possibility for faster charging of smartphone batteries.

Power miniaturization

The design of small power supplies requires engineers to find a balance between style and efficiency, while ensuring compliance with multiple electrical standards and safety requirements. Switch Mode Power Supplies (SMPS) have become a common solution for devices such as laptops because their high efficiency significantly reduces power consumption and heat dissipation, allowing them to be packaged in smaller enclosures.

As SMPS designs have matured, quasi-resonant switching converters (QRCs) operating in discontinuous conduction mode (DCM) have become the preferred topology for high-density AC-DC designs as it alleviates development challenges and provides more stable Loop control over other options. Quasi-resonant switching converters (also known as variable frequency or valley-switching flybacks) use parasitic resonance properties to control the turn-on voltage of the switching MOSFETs, thereby reducing switching losses (Figure 1).

FFRZVS circuit design scheme for USB PD adapter
Figure 1. The basic operation of a quasi-resonant switching converter illustrates how it uses parasitic resonance characteristics to control the turn-on voltage of a switching MOSFET.Source: Infineon

Figure 1B shows the resonant oscillation in the Vds waveform, which is caused by parasitic inductance, capacitance (L leakage) and CD. Resonance results in a “valley” point in Vds, and in quasi-resonant (QR) or valley-switched flyback, the circuit controller is configured to turn on the MOSFET at the minimum valley point. The controller can be programmed to turn on at different valley points. It’s always where the first valley opens, which is called a free-running QR flyback. In this mode, the resonant frequency and switching frequency vary with load, with minimum frequencies at higher loads.

Despite the advantages, the QRC design needs to be further optimized to achieve the density required for USB miniaturization. Although in the low-line case the MOSFET actually operates in zero voltage switching (ZVS) mode, this is not the case in the high-line case, which results in considerable switching losses. The basic QRC design can be modified to help reduce these losses. A slow reverse recovery diode can push some of the dissipated energy back into the bulk capacitor or output (Figure 1A). It is important to note that although this approach reduces losses at high line inputs, it results in higher losses at low line inputs.

Design considerations, such as using MOSFETs with higher output capacitance (COSS) and low Rds(ON) devices, can also help limit conduction and leakage losses. However, the relationship between load and switching frequency creates further difficulties for the QRC topology due to suboptimal transformer utilization at peak power levels. This phenomenon is the cause of common mode noise interference in touch screen applications.

As the pressure on power adapter size increases, manufacturers have begun to simplify production by incorporating windings into the PCB. It requires switching frequencies above 100 kHz to minimize copper losses. In this case, the Forced Frequency Resonant Zero Voltage Switching (FFRZVS) design provides the best solution.

In these designs, switching is implemented at the zero-voltage point of the primary transformer. It reduces conduction losses and heat dissipation in the power switch and increases efficiency. The high-frequency operation of the FFRZVS circuit can reduce the size of the magnetic components, enabling high-density and compact power supplies.

How FFRZVS Works

By making small changes to the basic QR design, the conduction losses of the FFRZVS can be significantly reduced and efficiency improved. These changes are shown in Figure 2, which shows the FFRZVS reference design based on the Infineon XDPS21071FFRZVS DCM controller.

FFRZVS circuit design scheme for USB PD adapter
Figure 2 The FFRZVS reference design is built around a flyback controller IC.Source: Infineon

Additional zero-voltage windings are added to the primary side of the circuit along with the main and auxiliary windings for zero-crossing detection. A zero-voltage winding ZWVS, along with a capacitor, power switch, QZVS, low-side gate driver, and RG1 are added to the circuit, enabling a self-controlled ZVS cycle.

FFRZVS circuit design scheme for USB PD adapter
Figure 3 This diagram shows the sequence of operations for the FFRZVS design.Source: Infineon

When the primary MOSFET QM turns off at t0, there is a short blanking period before the synchronous rectifier QSR turns on, causing current to flow through the secondary winding WS. When this field current drops to zero, the QSR turns off at t1 and the resonant circuit on the primary side winding induces oscillations around the voltage Vbulk. At time t2, the ZVS MOSFET is turned on, allowing the extra winding ZVS to function. Turning on ZVS at the main MOSFET resonant peak where the field current is zero results in a negative field current.

Once this current peaks at t3, the ZVS MOSFET turns off again, reversing the magnetizing current. This releases the equivalent capacitance, which causes the drain voltage of the main MOSFET to reach a minimum value at t4 turn-on. Turning on at the point where its drain-source voltage is lowest will result in a much lower conduction loss, approaching that of a true ZVS.

The above description highlights the important role the controller plays in the implementation of FFRZVS, which determines timing accuracy based on measurements of the output voltage.

FFRZVS for USB PD Adapter

The reference design of the USB PD adapter based on this working principle is shown in Figure 4. The fixed frequency ZVS controller used is specifically designed for high density power adapter applications. It is capable of operating in multiple modes including Discontinuous Conduction Mode (DCM), ZVS, Frequency Down Mode (FRM) and Burst Mode (BM) to ensure efficiency under different line and load conditions.

Figure 4 The reference design of the USB PD adapter is based on the working principle of FFRZVS.Source: Infineon

Digital and analog peripherals support various signal sampling and conditioning techniques required for flyback operation. The built-in high-voltage startup unit makes the IC power supply more efficient and flexible during no-load operation, and the high-voltage circuit provides voltage monitoring as well as undervoltage and undervoltage protection.

Mode switching and timing control are handled by a nano-DSP with configurable non-volatile OTP memory. This programmable capability simplifies PCB layout and reduces bill of materials.

FFRZVS circuit design scheme for USB PD adapter
Figure 5 This reference design achieves over 90% efficiency.Source: Infineon

The reference design also achieves a power density of 15 W/in3 in a 55(L) × 25(W) × 25(H) mm form factor (Figure 5). The adapter has been proven to withstand the worst 560V peak on the primary side. In terms of heat generation, the component temperature does not exceed 100°C.

Emission testing on this adapter has confirmed compliance with EN 55022 (CISPR 22) Class B test standards due to configurable frequency jitter, which helps improve EMI signals at heavy loads and maximum switching frequencies. The adapter also fully meets standby power requirements; the 45 W design consumes less than 30 mW of standby power at all AC input voltages. The design can also be easily scaled to support power output levels up to 65 W.

Wang Zan is a senior personnel engineer at Infineon Technologies.

The Links:   NL10276BC30-18L SN74AHCT16240DGVR

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